Sub-10 nm graphene nanoribbon lattices

ABSTRACT

A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.13/586,527, filed Aug. 15, 2012 the entire content and disclosure ofwhich is incorporated herein by reference.

BACKGROUND

The present disclosure relates to semiconductor device manufacturing,and more particular to methods of forming graphene lattices that includean ordered array of graphene nanoribbons, wherein each nanoribbon in theordered array has a uniform sub-10 nm width. The present disclosure alsorelates to a semiconductor structure including such an ordered array ofgraphene nanoribbons.

Several trends presently exist in the semiconductor and electronicsindustry including, for example, devices are being fabricated that aresmaller, faster and require less power than the previous generations ofdevices. One reason for these trends is that personal devices such as,for example, cellular phones and personal computing devices, are beingfabricated that are smaller and more portable. In addition to beingsmaller and more portable, personal devices also require increasedmemory, more computational power and speed. In view of these ongoingtrends, there is an increased demand in the industry for smaller andfaster transistors used to provide the core functionality of theintegrated circuits used in these devices.

Accordingly, in the semiconductor industry there is a continuing trendtoward fabricating integrated circuits (ICs) with higher densities. Toachieve higher densities, there has been, and continues to be, effortstoward down scaling the dimensions of the devices on semiconductorwafers generally produced from bulk silicon. These trends are pushingthe current technology to its limits. In order to accomplish thesetrends, high densities, smaller feature sizes, smaller separationsbetween features, and more precise feature shapes are required inintegrated circuits (ICs).

Significant resources go into down scaling the dimensions of devices andincreasing packing densities. For example, significant time may berequired to design such down scaled transistors. Moreover, the equipmentnecessary to produce such devices may be expensive and/or processesrelated to producing such devices may have to be tightly controlledand/or be operated under specific conditions. Accordingly, there aresignificant costs associated with exercising quality control oversemiconductor fabrication.

In view of the above, the semiconductor industry is pursuing graphene toachieve some of the aforementioned goals. Graphene, which is essentiallya flat sheet of carbon atoms, is a promising material for radiofrequency (RF) transistors and other electronic transistors. In orderfor graphene to be considered as a viable candidate for scaledsemiconductor devices, particularly for digital circuits, there exists aneed for providing a graphene lattice including an ordered array ofgraphene nanoribbons having sub-10 nm widths thereby opening up asignificant bandgap to realize a suitable on-off current ratio.

SUMMARY

A graphene lattice comprising an ordered array of graphene nanoribbonsis provided in which each graphene nanoribbon in the ordered array has awidth that is less than 10 nm. By “ordered array” it is meant thegraphene nanoribbons have a well defined repeating pattern associatedtherewith. The graphene lattice including the ordered array of graphenenanoribbons is formed by utilizing a layer of porous anodized alumina asa template which includes dense alumina portions and adjacent amorphousalumina portions. The amorphous alumina portions are removed and theremaining dense alumina portions which have an ordered latticearrangement are employed as an etch mask. After removing the amorphousalumina portions, each dense alumina portion has a width which is alsoless than 10 nm.

In one aspect of the present disclosure, a method of forming asemiconductor structure is provided. In this aspect of the presentdisclosure, the method includes forming a blanket layer of graphene onan exposed surface of a copper substrate. A blanket layer of aluminum isthen formed on an exposed surface of the blanket layer of graphene. Insome embodiments, an adhesion or seed layer, for example titanium oxide,can be formed on the exposed surface of the blanket layer of grapheneprior to forming the blanket layer of aluminum. Next, the blanket layerof aluminum is pre-patterned to form a plurality of regularly spacedpits within the blanket layer of aluminum. The pre-patterned blanketlayer of aluminum having the plurality of regularly spaced pits is thenconverted into a layer of porous anodized alumina. The layer of porousanodized alumina that is formed by this converting comprises a pluralityof alumina portions of a first density and having an ordered latticearrangement (i.e., well defined repeating pattern), and amorphousalumina portions of second density that are adjacent to the plurality ofalumina portions. In accordance with an aspect of the presentdisclosure, the first density of the plurality of alumina portions isgreater than the second density of the adjacent amorphous aluminaportions. Next, the adjacent amorphous alumina portions are removed fromthe layer of porous anodized alumina. At this point of the presentdisclosure, each alumina portion of the first density has a width ofless than 10 nm. Exposed portions of the blanket layer of graphene arethen removed using the plurality of alumina portions as an etch mask toprovide a graphene lattice comprising an ordered array of graphenenanoribbons, each graphene nanoribbon within the ordered array has awidth of less than 10 nm. Next, the etch mask is removed and theremaining graphene lattice including the ordered array of graphenenanoribbons is transferred to a substrate.

In another aspect of the present disclosure, a method of forming asemiconductor structure is provided. In this another aspect of thepresent disclosure, the method includes providing a structurecomprising, from bottom to top, a blanket layer of silicon carbide, ablanket layer of titanium located on an exposed surface of the blanketlayer of silicon carbide, and a blanket layer of aluminum located on anexposed surface of the blanket layer of titanium. Next, the blanketlayer of aluminum is pre-patterned to form a plurality of regularlyspaced pits within the blanket layer of aluminum. The pre-patternedblanket layer of aluminum having the plurality of regularly spaced pitsis then converted into a layer of porous anodized alumina. The layer ofporous anodized alumina that is formed by this converting comprises aplurality of alumina portions of a first density and having an orderedlattice arrangement, and amorphous alumina portions of a second densitythat are adjacent to the plurality of alumina portions. In accordancewith an aspect of the present disclosure, the first density of theplurality of alumina portions is greater than the second density of theadjacent amorphous alumina portions. Next, the adjacent amorphousalumina portions are removed from the layer of porous anodized alumina.At this point of the present disclosure, each alumina portion of thefirst density has a width of less than 10 nm. Exposed portions of theblanket layer of titanium and underlying portions of the blanker layerof silicon carbide are then removed using the plurality of aluminaportions as an etch mask to provide an ordered array of silicon carbideportions, each silicon carbide portion of the ordered array of siliconcarbide portions has a width of less than 10 nm. The etch mask andremaining portions of the blanket layer of titanium are removed. Next, alayer of graphene is formed on all exposed surfaces of each siliconcarbide portion. In accordance with the present disclosure each layer ofgraphene has a width of less than 10 nm. In this embodiment, each layerof graphene forms a graphene nanoribbon.

In yet another aspect of the present disclosure, a semiconductorstructure is provided. The semiconductor structure that is provided inthe present disclosure includes a graphene lattice comprising an orderedarray of graphene nanoribbons located on a surface of a substrate,wherein each graphene nanoribbon of the ordered array of graphenenanoribbons has a width of less than 10 nm.

In a further embodiment of the present disclosure, another semiconductorstructure is provided. The semiconductor structure of this furtherembodiment includes an ordered array (well defined repeating pattern) ofsilicon carbide portions located on a surface of a substrate. Eachsilicon carbide portion of the ordered array of silicon carbide portionshas a width which is less than 10 nm. The structure also includes atleast a layer of graphene located on a topmost surface of each of thesilicon carbide portions. Each layer of graphene has a width of lessthan 10 nm. In this embodiment, each layer of graphene is representativeof a graphene nanoribbon within an ordered array of graphenenanoribbons.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial representation (through a cross sectional view)illustrating a structure including a blanket layer of graphene formed onan exposed surface of a copper substrate that can be employed in oneembodiment of the present disclosure.

FIG. 2 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 1 after forming a blanket layer ofaluminum on an exposed surface of the blanket layer of graphene.

FIG. 3 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 2 after pre-patterning the blanketlayer of aluminum to form pits within the blanket layer of aluminum thathave a desired lattice periodicity.

FIG. 4 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 3 after converting the pre-patternedblanket layer of aluminum into a layer of porous anodized alumina.

FIG. 5 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 4 after removing amorphous portionsof the layer of porous anodized alumina, while maintaining dense aluminaportions that have a sub-10 nm width.

FIG. 6 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 5 after etching portions of theblanket layer of graphene using the dense alumina portions of the layerof porous anodized alumina as an etch mask.

FIG. 7 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 6 after removing the dense aluminaportions of the layer of porous anodized alumina and application of ahandle substrate thereto.

FIG. 8 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 7 after removing the coppersubstrate, transferring the remaining structure to a substrate andremoving the handle substrate therefrom.

FIG. 9 is a pictorial representation (through a cross sectional view)illustrating a structure including a substrate, and a blanket layer ofsilicon carbide formed on an exposed surface of the substrate that canbe employed in one embodiment of the present disclosure.

FIG. 10 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 9 after forming a blanket layer oftitanium on an exposed surface of the blanket layer of silicon carbideand a blanket layer of aluminum on an exposed surface of the blanketlayer of titanium.

FIG. 11 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 10 after pre-patterning the blanketlayer of aluminum to form pits within the blanket layer of aluminum thathave a desired lattice periodicity.

FIG. 12 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 11 after converting the pre-patternedblanket layer of aluminum into a layer of porous anodized alumina.

FIG. 13 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 12 after removing amorphous portionsof the layer of porous anodized alumina, while maintaining dense aluminaportions that have a sub-10 nm width.

FIG. 14 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 13 after etching exposed portions ofthe blanket layer of titanium and at least underlying portions of theblanket layer of silicon carbide forming a silicon carbide lattice usingthe dense alumina portions of the layer of porous anodized alumina as anetch mask.

FIG. 15 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 14 after removing the dense aluminaportions of the layer of porous anodized alumina and the remainingportions of the blanket layer of titanium from the structure.

FIG. 16 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 15 after forming a layer of grapheneon exposed surfaces of each silicon carbide lattice.

DETAILED DESCRIPTION

The present disclosure, which provides highly ordered, sub-10 nmgraphene lattice structures and methods of forming the same, will now bedescribed in greater detail by referring to the following discussion anddrawings that accompany the present application. It is noted that thedrawings of the present application are provided for illustrativepurposes and, as such, they are not drawn to scale. In the drawings andthe description that follows, like elements are referred to by likereference numerals. For purposes of the description hereinafter, theterms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”,“top”, “bottom”, and derivatives thereof shall relate to the components,layers and/or elements as oriented in the drawing figures whichaccompany the present application.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill in the art that the present disclosure may bepracticed with viable alternative process options without these specificdetails. In other instances, well-known structures or processing stepshave not been described in detail in order to avoid obscuring thevarious embodiments of the present disclosure.

In order for graphene to be considered as technology relevant materialfor digital applications, the graphene must be trimmed in some fashioninto nanoribbons with sub-10 nm widths thereby opening up a significantbandgap to realize a suitable on-off current ratio. Highly accurate andreproducible definition of the nanoribbon widths in this sub-10 nmregime is a key to produce reliable nanoelectronic devices fromgraphene. The primary problem with existing graphene structures, such asgraphene nanoribbons or nanomesh, tailored to accomplish this task isthat they result in an unacceptable statistical variability in ribbonwidth when the devices are scaled aggressively since the bandgap isinversely proportional to the ribbon width in this regime. Ultimately, adensely packaged graphene lattice structure with periodic patterningwould provide a suitable means of enabling both small reproduciblefeatures to enable a suitable bandgap and a higher current drive—twofeatures that are highly desirable for nanoelectronic devices, e.g., agraphene based field effect transistor (FET).

To date, graphene nanoribbons and nanomesh are the two most prominentand effective examples for the successful creation of a bandgap at roomtemperature in graphene. Graphene nanoribbons have been produced usingdifferent approaches. In a broad sense, the primary problems withcurrently conceived methods to create individual graphene nanoribbonsare low drive current, or conductance, coupled with a tradeoff betweenreaching the sub-10 nm regime and overcoming the placement problem.

Accordingly, the present disclosure creates highly-ordered graphenelattices which contain sub-10 nm graphene nanoribbons. Hexagonal, squareand triangular as well as hybridized lattice arrangements of nanoribbonscan be formed by using one of the methods of the present disclosure. By“hybridized lattice arrangements” it is meant lattices containingarrangements of at least one of the aforementioned shapes as well asdiamond shapes. The graphene lattices that can be obtained in thepresent disclosure have independently tunable periodicity and ribbonwidths with a narrow distribution. By “narrow distribution” it ismeant±1 nm. The graphene nanoribbons within the graphene latticestructure of the present disclosure promote high current levels andthroughput, controllable bandgap formation and a variety of possiblelattice arrangements with sub-10 nm features that potentially may giverise to unique properties, lending the graphene lattice structures ofthe present disclosure to a broad range of nanoelectronic applications.These sub-10 nm lattice structures are not possible utilizing any of theprior art techniques.

Reference is now made to FIGS. 1-8 which illustrate one embodiment ofthe present disclosure for forming a semiconductor structure includingan ordered array of sub-10 nm graphene nanoribbons. Specifically, thisembodiment of the present disclosure provides a graphene latticecomprising an ordered array of graphene nanoribbons located on a surfaceof a substrate, wherein each graphene nanoribbon of the ordered array ofgraphene nanoribbons has a width which is less than 10 nm.

Each graphene nanoribbon of the ordered array of graphene nanoribbonscomprises graphene. The term “graphene” as used throughout the presentdisclosure denotes a one-atom-thick planar sheet of sp²-bonded carbonatoms that are densely packed in a honeycomb crystal lattice. Thegraphene employed in the present disclosure has a two-dimensional (2D)hexagonal crystallographic bonding structure.

Reference is first made to FIG. 1, which illustrates a structureincluding a blanket layer of graphene 12 formed on an exposed surface ofa copper substrate 10 that can be employed in one embodiment of thepresent disclosure.

The copper substrate 10 that can be employed in the present disclosurecan be a copper foil that can be optionally present on another substrate(not shown in the drawing). The another substrate that is not shown inthe drawings can be any semiconductor material, dielectric material,conductive material, or any multilayered stack thereof.

The copper substrate 10 can be formed utilizing any deposition processwell known to those skilled in the art. For example, a copper substrate10 can be formed by chemical vapor deposition, plasma enhanced chemicalvapor deposition, physical vapor deposition, sputtering, plating,chemical solution deposition and electroless plating. Typically, copperfoils are formed by sputtering a copper foil from a copper-containingtarget.

In one embodiment, the copper substrate 10 has a thickness from 7 μm to25 μm. In another embodiment, the copper substrate 10 has a thicknessfrom 20 μm to 30 μm. Other thicknesses for the copper substrate 10 thatare above and/or below the thickness ranges mentioned above can also beused in the present disclosure.

The blanket layer of graphene 12 is a contiguous layer of graphene thatcan be comprised of single-layer graphene (nominally 0.34 nm thick),few-layer graphene (2-10 graphene layers), multi-layer graphene (>10graphene layers), a mixture of single-layer, few-layer, and multi-layergraphene, or any combination of graphene layers mixed with amorphousand/or disordered carbon phases that result by graphene formation atlower temperatures (between 200° C. and 900° C.). The blanket layer ofgraphene 12 can also include, if desired, substitutional (where C atomsin graphene are replaced with dopant atoms covalently bonded to nextnearest neighbor, nnn, atoms), and dopant atoms or molecules that do notform covalent bonds to graphene and lie on top of the graphene layer orbetween graphene layers in the case few layer or multilayer intercalatedgraphene. Typically, the blanket layer of graphene that is formed on thecopper substrate 10 is single-layer graphene.

The blanket layer of graphene 12 can be formed utilizing a depositionprocess such as, for example, chemical vapor deposition (CVD), plasmaenhanced chemical vapor deposition (PECVD), and ultraviolet (UV)assisted CVD. In one embodiment, the blanket layer of graphene is formedby CVD. The deposition process that can be employed in the presentdisclosure, which may be referred as a selective deposition process or acatalytic growth process, is initiated on the exposed surfaces of thecopper substrate 10. In one embodiment, the deposition of the blanketlayer of graphene 12 on the exposed surface of the copper substrate 10can be performed at a temperature up to, but not exceeding, 500° C. forPECVD. In another embodiment, the growth of graphene occurs at atemperature from 800° C. to 1080° C. The deposition process that can beused in the present disclosure for forming the blanket layer of grapheneincludes utilizing any known carbon sources including, for example,benzene, propane, ethane and other hydrocarbons, and othercarbon-containing gases.

In one embodiment of the present disclosure, the blanket layer ofgraphene 12 can have a thickness from 0.34 nm to 0.8 nm. In anotherembodiment, the blanket layer of graphene 12 can have a thickness from0.7 nm to 3.4 nm. The blanket layer of graphene 12 can have otherthicknesses that are above the ranges mentioned above.

Referring to FIG. 2, there is depicted the structure of FIG. 1 afterforming a blanket layer of aluminum 14 on an exposed surface of theblanket layer of graphene 12. The blanket layer of aluminum 14 can beformed utilizing any conventional deposition process. Examples ofdeposition processes that can be used in the present disclosure include,but are not limited to, chemical vapor deposition, atomic layerdeposition, plasma enhanced chemical vapor deposition, physical vapordeposition, sputtering, plating, chemical solution deposition andelectroless plating. In one embodiment, atomic layer deposition is usedto provide a blanket layer of aluminum that has a surface roughness ofabout 20 nm RMS or less.

In one embodiment, the blanket layer of aluminum 14 that can be employedin the present disclosure has a thickness from 50 nm to 500 nm. Inanother embodiment, the blanket layer of aluminum 14 can have athickness from 100 nm to 1000 nm. The blanket layer of aluminum 14 canhave other thicknesses that are above or below the ranges mentionedabove.

In some embodiments of the present disclosure (not shown), an adhesionor seed layer, for example, titanium oxide, is formed between theblanket layer of graphene and the blanket layer of aluminum. Whenpresent, the adhesion or seed layer can be formed by a depositionprocess. Suitable deposition processes that can be used in the presentdisclosure to form the adhesion or seed layer include, but are notlimited to, chemical vapor deposition, atomic layer deposition plasmaenhanced chemical vapor deposition, physical vapor deposition,sputtering, plating, chemical solution deposition and electrolessplating. In one embodiment, the adhesion or seed layer that can beemployed in the present disclosure has a thickness from 3 nm to 10 nm.In another embodiment, the adhesion or seed layer can have a thicknessfrom 5 nm to 50 nm.

Referring now to FIG. 3, there is illustrated the structure of FIG. 2after pre-patterning the blanket layer of aluminum 12 to form apre-patterned blanket layer of aluminum 14′ that has pits 16 formedtherein that have a desired lattice periodicity, i.e., spacing betweenpits. That is, FIG. 3 illustrates the structure of FIG. 2 after forminga plurality of regularly spaced pits 16 within the blanket layer ofaluminum 14. The regularly spaced apart pits 16 serve as initiationsites for pore generation at the initial stage of a subsequentlyperformed anozidation process.

In one embodiment of the present disclosure, the pre-patterned blanketlayer of aluminum 14′ including the plurality of regular spaced apartpits 16 can be formed by nanoimprintation. Nanoimprintation is a lowcost, high throughput and high resolution nanolithography process inwhich patterns can be created into the blanket layer of aluminum 14 byindentation using an imprint resist or mold.

In another embodiment, the pre-patterned blanket layer of aluminum 14′including the plurality of regular spaced apart pits 16 can be formed byinterference lithography followed by an aluminum etch. Interferencelithography is a technique for patterning regular arrays of finefeatures, without the use of complex optical systems or photomasks. Itsuch a process, an interference pattern between two or more coherentlight waves is set up and recorded in a photoresist layer. Thephotoresist layer (not shown) is formed atop the blanket layer ofaluminum 14 utilizing conventional deposition process such as spin-oncoating. The interference pattern consists of a periodic series offringes representing intensity minima and maxima. Upon post-exposurephotolithographic processing, a photoresist pattern corresponding to theperiodic intensity pattern emerges. For 2-beam interference, thefringe-to-fringe spacing or period is given by (λ2)/sin(θ/2), where λ isthe wavelength and θ is the angle between the two interfering waves. Theminimum period achievable is then half the wavelength. By using 3-beaminterference, arrays with hexagonal symmetry can be generated, whilewith 4 beams, arrays with rectangular symmetry are generated. Hence, bysuperimposing different beam combinations, different patterns are madepossible. The aluminum etch that follows the interference lithographicincludes an etchant the selectively removes exposed portions of theblanket layer of aluminum 14 relative to the patterned photoresist. Inone embodiment, the etchant that forms the pits 16 into the blanketlayer of aluminum 14 comprises Aluminum Etchant Type A from TranseneCompany, Inc. After etching, the patterned resist can be removed by aconventional resist stripping process such as, for example, ashing.

Referring to FIG. 4, there is illustrated the structure of FIG. 3 afterconverting the pre-patterned blanket layer of aluminum 14′ into a layerof porous anodized alumina 18. The converting is performed utilizing anAl anodization process. The layer of porous anodized alumina 18comprises a plurality of pores 19 which are surrounded by two distinctoxides of aluminum.

Specifically, the two distinct oxides of aluminum which surround eachpore include an outer cell wall portion that is comprised of amorphousalumina and an inner cell wall portion that is comprised of densealumina portions that is mechanically compressed by the competingexpansion of adjacent pores 19. In particular, the layer of porousanodized alumina 18 that is formed comprises a plurality of aluminaportions 18 d (hereinafter referred to as dense alumina portions 18 d)of a first density and having an ordered lattice arrangement, andamorphous alumina portions of a second density which are adjacent to thedense alumina portions 18 d. The amorphous alumina portions 18 a arepositioned between the pores 19 and the dense alumina portions 18 d. Inaccordance with the present disclosure, the first density of the densealumina portions 18 d is greater than the second density of theamorphous alumina portions 18 a.

The plurality of pores 19 are spaced apart by an equal interporedistance, D_(int). The interpore distance is the distance measure from acenter of one pore to a center of a nearest neighboring pore. Theinterpore distance is dependent on the conditions used to during theanozidation process. In one embodiment, the interpore distance can befrom 45 nm to 100 nm. In another embodiment, the interpore distance canbe from 100 nm to 200 nm. In yet a further embodiment, the interporedistance can be from 200 nm to 500 nm.

Each pore 19 that is formed has a characteristic shape which isdependent on the anodization conditions employed. In one embodiment,each pore 19 has a circular shape; circular shaped pores typicallyprovide hexagonal lattices. In another embodiment, each pore 19 has asquare shape. In yet another embodiment, each pore has a triangularshape. Also, and in yet other embodiments of the present disclosure,each pore 19 has a diamond shape. The shape of the pores 19 and thelattice arrangement of the dense alumina portions 18 d within the porousanodized alumina layer 18 are dictated by the positioning of the pits 16formed in the pre-patterned blanket layer of aluminum 14′. The latticearrangement of the subsequently formed graphene nanoribbons are in turndictated by the lattice arrangement of the dense alumina portions 18 dwithin the porous anodized alumina layer 18. The pores 19 that areformed can have a porosity from 8 to 12%.

In one embodiment, each dense alumina portion 18 d has a width, w₁, ofless than 10 nm. In another embodiment, each dense alumina portion 19 dhas a width, w₁, from 7 nm to 55 nm.

As mentioned above, the pre-patterned blanket layer of alumina 14′ isconverted into the layer of porous anodized alumina 18 utilizing analuminum anodization process which oxidizes the blanket layer ofaluminum 14. In this embodiment of the present disclosure, the blanketlayer of graphene 12 and copper substrate 10 serve as an electrode inthe anodization process. The anodization process that can be used inpresent disclosures includes a bath containing an electrolyte. Thestructure shown in FIG. 2 is immersed in the bath and a potential isapplied at an anozidation temperature. The other electrode of theanozidation process can be added to the bath prior to anozidation.

The electrolyte includes any acid that is capable of oxidizing aluminum.Examples of suitable electrolytes that can be used in the presentdisclosure include, but are not limited to, sulfuric acid, oxalic acid,phosphoric acid, gylolic acid, tartaric acid, malic acid and citricacid.

The concentration of the acid within the bath varies depending on thetype of acid employed. In one embodiment, the concentration of acidwithin the bath can be from 0.1 to 15 volume % of the total bath, theremaining portion of the bath may include water. In another embodimentof the present disclosure, the concentration of acid within the bath canbe from 0.2 to 12 volume % of the total bath, the remaining portion ofthe bath may include water.

The applied potential that can be used during anozidation can varydepending on the type of acid employed. Typically, the applied potentialranges from 8 Volts to 500 Volts. In one embodiment, the appliedpotential that can be used during the anozidation process is from 8Volts to 45 Volts. In another embodiment, the applied potential that canbe used during the anozidation process is from 40 Volts to 100 Volts. Inyet another embodiment, the applied potential that can be used duringthe anozidation process is from 80 Volts to 500 Volts.

The anozidation temperature that can be employed during the anozidationprocess can also be varied. In one embodiment, the anozidationtemperature can be from 250° Kelvin to 300° Kelvin. In anotherembodiment, the anozidation temperature can be from 270° Kelvin to 298°Kelvin.

The following table provides some exemplary conditions that can be usedduring the anozidation process.

TABLE 1 Exemplary Anozidation Conditions Electrolyte PotentialConcentration Range Temperatures Electrolyte (volume %) (Volts) (K)Sulfuric acid  5-10  8-70 273-288 Oxalic acid 0.25-3.0   40-160 274-288Phosphoric acid  1-10  60-235 273-277 Glycolic acid  1-10  60-150283-293 Tartaric acid 2-4 235-240 278 Malic acid 2-4 220-450 283-293Citric acid 2-4 270-370 293

Referring now to FIG. 5, there is illustrated the structure of FIG. 4after removing the amorphous alumina portions 18 a of the layer ofporous anodized alumina 18, while maintaining the dense alumina portions18 d. In some embodiments, the dense alumina portions can have a sub-10nm width at this point of the present disclosure, in other embodiments,the sub-10 nm width of the dense alumina portions 18 d occurs during theremoval of the amorphous alumina portions from the layer of porousanodized alumina. Moreover, the remaining dense alumina portions 18 d ofthe layer of porous anodized alumina have the ordered latticearrangement provided by the pores 19 previously formed into thepre-patterned blanket layer of aluminum 14′.

The selective removal of the amorphous alumina portions 18 a can beperformed utilizing a chemical wet etching process in which an acid isused as the etchant. In one embodiment, the etchant can be dilutephosphoric acid. In another embodiment, the etchant can be dilutechromic acid. In some embodiments, the width of each of the remainingdense alumina portions 18 d can be thinned at this point of the presentdisclosure to a range that is sub-10 nm.

Referring now to FIG. 6, there is illustrated the structure of FIG. 5after etching portions of the blanket layer of graphene 12 using thedense alumina portions 18 d of the layer of porous anodized alumina 18as an etch mask. That is, exposed portions of the blanket layer ofgraphene 12 which are not protected by the remaining dense aluminaportions 18 d are removed providing graphene nanoribbons 12′ locatedbeneath the remaining dense alumina portions 18 d. In one embodiment,the removal of the exposed portions of the blanket layer of graphene 12can be performed utilizing oxygen plasma etching. This process providesa graphene lattice comprising an ordered array of graphene nanoribbonsthat have the same lattice arrangement as that of the overlying densealumina portions 18 d. Moreover, each graphene nanoribbon 12′ within theordered array of graphene nanoribbons has a width which is below 10 nm.Typically, the width of each graphene nanoribbon 12′ that is formed isfrom 4 nm to 9 nm. In some embodiments, each graphene nanoribbon canhave a same sub-10 nm width.

Referring now to FIG. 7, there is illustrated the structure of FIG. 6after removing the dense alumina portions 18 d of the layer of porousanodized alumina 18 and application of a handle substrate 20 to thesurface of the copper substrate 10 which contains the graphenenanoribbons 12′. The dense alumina portions 18 d can be removed byutilizing a wet etch process in which a chemical etchant thatselectively removes the dense alumina portions 18 d relative to theunderlying graphene layer and copper substrate 10 is employed. In oneembodiment, the chemical etchant that can be used to remove theremaining dense alumina portions 18 d comprises a dilute chromic acidmixture.

After removing the dense alumina portions 18 d from the structure, ahandle substrate 20 is applied to the surface of the copper substrate 10that includes the ordered array of graphene nanoribbons 12′. The handlesubstrate 20 can be any material (flexible or non-flexible) includingfor example, a polymer such as polymethaacylate (PMMA). Other types ofmaterials such as, for example, HD 3007 on a rigid substrate can be usedas the handle substrate 20. The handle substrate 20 can be applied tothe copper substrate 10 by utilizing any conventional deposition processincluding, for example, spin-on coating. The thickness of the handlesubstrate 20 that can be employed in the present disclosure may vary solong as the handle substrate 20 covers the topmost surface of each ofthe graphene nanoribbons 12′.

Referring to FIG. 8, there is illustrated the structure of FIG. 7 afterremoving the copper substrate 10, transferring the remaining structureto a substrate 22 and removing the handle substrate 20 from thestructure so as to expose the graphene nanoribbons 12′. The coppersubstrate 10 can be removed from the structure shown in FIG. 7 byutilizing a wet etch process in which a chemical etchant thatselectively removes the copper substrate 10 relative to the underlyinggraphene nanoribbons 12′ and handle substrate 20 is employed. In oneembodiment, the chemical etchant that can be used to remove the coppersubstrate 10 comprises a ferric chloride solution.

The graphene nanoribbons on the handle substrate 20 are then transferredto substrate 22. In one embodiment, substrate 22 is comprised of a bulksemiconductor material. In another embodiment, and as shown, thesubstrate 22 can be comprised of a top insulator layer 26 and a bottomsemiconductor layer 24. In such an embodiment, an interface is formedbetween the top insulator layer 26 and the graphene nanoribbons 12′. Thebulk semiconductor and the bottom semiconductor layer can be comprisedof any semiconductor material including, for example, Si, SiGe, SiC,SiGeC, GaAs, and InP. The top insulator layer 26 can be comprised of asemiconductor oxide, nitride and/or oxynitride. In one embodiment, thetop insulator layer 26 is comprised of silicon oxide and the bottomsemiconductor layer is comprised of silicon.

The transfer of the graphene nanoribbons 12′ on the handle substrate 20to substrate 22 can be performed utilizing a bonding process. After thetransfer of the graphene nanoribbons 12′ to substrate 22, the handlesubstrate 20 can be removed utilizing, for example, a combination ofacetone and isopropyl alcohol in the case of PMMA.

Still referring to FIG. 8, there is shown one exemplary semiconductorstructure of the present disclosure which includes an ordered array ofgraphene nanoribbons located on a surface of a substrate 22, whereineach graphene nanoribbon 12′ of the ordered array of graphenenanoribbons has a width, w₂, which is less than 10 nm. In oneembodiment, the width of each of the graphene nanoribbons 12′ within theordered array is from 4 nm to 9 nm.

It is also noted that the ordered array of graphene nanoribbons ispresent in a lattice arrangement which mimics that of the dense aluminaportions 18 d formed during the anodization process as a result of therelative positions of the plurality of pits 16 formed in thepre-patterned aluminum layer 14′. Thus, the ordered array of graphenenanoribbons can be present as a hexagonal arrangement, a squarearrangement, a triangular arrangement or hybridized arrangement.

Also, and as shown in FIG. 8, each graphene nanoribbon 12′ of theordered array of graphene nanoribbons has a bottommost surface that isdirect contact with a surface portion of the substrate 22, wherein thesurface portion of the substrate 22 is coplanar with other surfaceportions of the substrate not including the graphene nanoribbons 12′.

At this point of the present disclosure, a semiconductor device can befabricating using the ordered array of graphene nanoribbons as elementas the device. For example, a field-effect transistor can be formed byforming a gate dielectric and a gate electrode on portions of theordered array of graphene nanoribbons. Other portions of the orderedarray of graphene nanoribbons can be fabricated to include source anddrain contacts of the field-effect transistor.

Reference is now made to FIGS. 9-16 which illustrate another method ofthe present disclosure. This method of the present disclosure begins byforming the structure shown in FIG. 9. The structure shown in FIG. 9includes a substrate 30, and a blanket layer of silicon carbide 32formed on an exposed surface of the substrate 30.

In one embodiment of the present disclosure, the substrate 30 caninclude a semiconductor material such as, for example, those mentionedabove for bottom semiconductor layer 24 of substrate 22. In anotherembodiment, the semiconductor substrate 30 can include an insulatorlayer such as for example, sapphire.

The blanket layer of silicon carbide 32 that is formed on the exposedsurface of the substrate 30 can be formed utilizing any depositionprocess. For example, an epitaxial growth process can be used in formingthe blanket layer of silicon carbide 32 on the exposed surface of thesubstrate 30. Other examples of deposition processes that can be used informing the blanket layer of silicon carbide 32 include chemical vapordeposition or plasma enhanced chemical vapor deposition. Alternatively,and in other embodiments, the blanket layer of silicon carbide 32 can betransferred to the substrate 30 utilizing a conventional layer transferprocess.

In one embodiment, the blanket layer of silicon carbide 32 has athickness from 5 nm to 100 nm. In another embodiment, the blanket layerof silicon carbide 32 has a thickness from 50 nm to 1000 nm.

Referring now to FIG. 10, there is illustrated the structure of FIG. 9after forming a blanket layer of titanium 33 on an exposed surface ofthe blanket layer of silicon carbide 32 and a blanket layer of aluminum14 on an exposed surface of the blanket layer of titanium 33.

The blanket layer of titanium 33 that is present on the exposed surfaceof the blanket layer of silicon carbide 32 can be formed utilizing anyconventional deposition process. Examples of deposition processes thatcan be used in the present disclosure to form the blanket layer oftitanium 33 include, but are not limited to, chemical vapor deposition,atomic layer deposition plasma enhanced chemical vapor deposition,physical vapor deposition, sputtering, plating, chemical solutiondeposition and electroless plating. In one embodiment, the blanket layerof titanium 33 that can be employed in the present disclosure has athickness from 3 nm to 10 nm. In another embodiment, the blanket layerof titanium 33 can have a thickness from 5 nm to 50 nm. The blanketlayer of titanium 33 can have other thicknesses that are above or belowthe ranges mentioned above. In this particular embodiment of the presentdisclosure, the blanket layer of titanium 33 serves as an electrode in asubsequently performed anozidation processing step.

The blanket layer of aluminum 14 can be formed utilizing one of thetechniques mentioned above in forming the blanket layer of aluminum inthe previously described embodiment of the present disclosure. Thethickness of the blanket layer of aluminum 14 used in this embodiment ofthe present disclosure is within the ranges mentioned above for theblanket layer of aluminum used in the previously described embodiment ofthe present disclosure.

Referring to FIG. 11, there is depicted the structure of FIG. 10 afterpre-patterning the blanket layer of aluminum 14 to provide apre-patterned blanket layer of aluminum 14′ that has a plurality of pits16 formed that have a desired lattice periodicity. The formation of thepits 16 within the blanket layer of aluminum includes one of thetechniques mentioned for forming the structure shown in FIG. 3.

Referring now to FIG. 12, there is illustrated the structure of FIG. 11after converting the pre-patterned blanket layer of aluminum 14′ into alayer of porous anodized alumina 18. The converting is performedutilizing the Al anodization process described above for forming thestructure shown in FIG. 4 of the present disclosure. The layer of porousanodized alumina 18 comprises a plurality of pores 19 which aresurrounded by two distinct oxides of aluminum, i.e., amorphous aluminaportions 18 a and dense alumina portions 18 d. These two distinct oxidesof aluminum and pores 19 formed in this embodiment can have any of thecharacteristics/properties mentioned above in forming the structureshown in FIG. 4. In some embodiments, the dense alumina portions 18 dcan have a sub-10 nm width at this point of the present disclosure.Alternatively, the sub-10 nm width within the dense alumina portions isprovided after removing the amorphous alumina portions from the layer ofporous anodized alumina.

Referring to FIG. 13, there is illustrated the structure of FIG. 12after removing the amorphous portions 18 a of the layer of porousanodized alumina 18, while maintaining the dense alumina portions 18 dthat have a sub-10 nm width and an ordered lattice arrangement. Theremoval of the amorphous alumina portions 18 a includes one of thetechniques mentioned above for forming the structure shown in FIG. 5.

Referring to FIG. 14, there is illustrated the structure of FIG. 13after etching exposed portions of the blanket layer of titanium 33 andat least underlying portions of the blanket layer of silicon carbide 32forming patterned titanium portions 33′ and an underlying siliconcarbide lattice made of individual silicon carbide portions 32′ usingthe dense alumina portions 18 d of the layer of porous anodized alumina18 as an etch mask. The silicon carbide lattice that is formed has asame lattice arrangement as that of the pores formed into the blanketlayer of aluminum by the anozidation process. The width of eachindividual silicon carbide portion 32′ of the lattice of silicon carbideportions is the same as that of the dense alumina portions 18 d. In thisstep of the present disclosure, a single etch or a plurality of etchingsteps can be used to transfer the pattern from the etch mask into theunderlying layers of titanium and silicon carbide. In one embodiment,reactive ion etching can be used to provide the structure illustrated inFIG. 14. In another embodiment, a chemical wet etching process can beused in providing the structure illustrate in FIG. 14. In a furtherembodiment, a combination of dry etching and/or wet etching can beemployed in providing the structure shown in FIG. 14.

Referring now to FIG. 15, there is illustrated the structure of FIG. 14after removing the dense alumina portions 18 d of the layer of porousanodized alumina 18 and the remaining portions of the blanket layer oftitanium (i.e., patterned titanium portions 33′) from the structure. Theremoval of the dense alumina portions 18 d may be performed utilizingthe same etch mentioned above for removing the same material from thestructure in FIG. 6. The underlying patterned titanium portions 33′ canbe then be removed utilizing an etching process that selectively removestitanium. For example, Titanium Etchant TFT (Transene Company, Inc.) canbe used to remove the remaining patterned titanium portions 33′ from thestructure. The structure shown in FIG. 15 includes silicon carbideportions 32′ that each has a bottommost surface that is direct contactwith a surface portion of substrate 30′, wherein the surface portion ofthe substrate 30′ is vertically offset from other surface portions ofthe substrate 30′ not including the silicon carbide portions 32′. Thesurface portion including the silicon carbide portions 32′ includespillar portions 31 that connect each surface portion of the substrateincluding a silicon carbide portion 32′ to a remaining portion of thesubstrate.

Referring to FIG. 16, there is illustrated the structure of FIG. 15after forming a layer of graphene 34 on exposed surfaces of each siliconcarbide portion 32′. The layer of graphene 34 can be formed utilizingone of the techniques mentioned above for forming the blanket layer ofgraphene 14. In this embodiment, the selective deposition occurs only onexposed surfaces of the silicon carbide portions 32′.

In this embodiment and as shown in FIG. 16, a semiconductor structure isprovided that includes an ordered array of silicon carbide portionslocated on a surface of a substrate 30′, wherein each silicon carbideportion 32′ of the ordered array of silicon carbide portions has a widthwhich is less than 10 nm. Also, the structure includes a layer ofgraphene 34 located on a topmost surface of each silicon carbide portion32′, wherein each layer of graphene 34 has a width of less than 10 nm.In one embodiment, the width of each layer of graphene 34 is from 4 nmto 9 nm.

In the illustrated structure, each layer of graphene 34 represents agraphene nanoribbon within an ordered array. The ordered array ofgraphene nanoribbons can have a hexagonal arrangement, a squarearrangement, a triangular arrangement or a hybridized arrangement. Also,in this embodiment, each layer of graphene 34 has a portion present onsidewall surfaces of each silicon carbide portion 32′. In someembodiments, not shown, a mask can be formed which prevents graphene togrow on the exposed sidewalls of each silicon carbide portion.

At this point of the present disclosure, a semiconductor device can befabricating using the ordered array of graphene nanoribbons as elementas the device. For example, a field effect transistor can be formed byforming a gate dielectric and a gate electrode on portions of theordered array of graphene nanoribbons. Other portions of the orderedarray of graphene nanoribbons can be fabricated to include source anddrain contacts of the field effect transistor.

While the present disclosure has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present disclosure. It is therefore intended that the presentdisclosure not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor structure comprising an orderedarray of graphene nanoribbons located on a surface of a substrate,wherein each graphene nanoribbon of the ordered array of graphenenanoribbons has a width which is less than 10 nm
 2. The semiconductorstructure of claim 1, wherein said width is from 4 nm to 9 nm.
 3. Thesemiconductor structure of claim 1, wherein said ordered array ofgraphene nanoribbons is present as a hexagonal arrangement.
 4. Thesemiconductor structure of claim 1, wherein said ordered array ofgraphene nanoribbons is present as a square arrangement.
 5. Thesemiconductor structure of claim 1, wherein said ordered array ofgraphene nanoribbons is present as a triangular arrangement.
 6. Thesemiconductor structure of claim 1, wherein each graphene nanoribbon ofsaid plurality of graphene nanoribbons has a bottommost surface that isdirect contact with a surface portion of said substrate, wherein saidsurface portion of said substrate is coplanar with other surfaceportions of said substrate not including said graphene nanoribbon. 7.The semiconductor structure of claim 6, wherein said substrate is a bulksemiconductor material.
 8. The semiconductor structure of claim 6,wherein said substrate includes a material stack of, from bottom to top,a semiconductor material and an insulator material.
 9. A semiconductorstructure comprising: an ordered array of silicon carbide portionslocated on a surface of a substrate, wherein each silicon carbideportion of the ordered array of silicon carbide portions has a widthwhich is less than 10 nm; and a layer of graphene located on a topmostsurface of each of said silicon carbide portions, wherein each layer ofgraphene has a width of less than 10 nm.
 10. The semiconductor structureof claim 9, wherein each layer of graphene collectively provides agraphene lattice having an ordered lattice arrangement.
 11. Thesemiconductor structure of claim 9, wherein said width of each layer ofgraphene is from 4 nm to 9 nm.
 12. The semiconductor structure of claim10, wherein said lattice arrangement is a hexagonal arrangement.
 13. Thesemiconductor structure of claim 10, wherein said lattice arrangement isa square arrangement.
 14. The semiconductor structure of claim 10,wherein said lattice arrangement is a triangular arrangement.
 15. Thesemiconductor structure of claim 9, wherein each layer of graphene has aportion present on sidewall surfaces of each silicon carbide portion.16. The semiconductor structure of claim 9, wherein each layer ofgraphene is present only on a top surface of each of said siliconcarbide portions
 17. The semiconductor structure of claim 9, whereineach silicon carbide portion of said plurality of silicon carbideportions has a bottommost surface that is direct contact with a surfaceportion of said substrate, wherein said surface portion of saidsubstrate is vertically offset from other surface portions of saidsubstrate not including said silicon carbide portions.
 18. Thesemiconductor structure of claim 16, wherein said substrate is sapphire.